Fault Tolerance Limits and Input Stimulus Selection using an Implemented FPGA-based Testing System

Vassios, Vasilios/ Pouros, Sotirios/ Papakostas, Dimitrios/ Παπακώστας, Δημήτριος/ Πούρος, Σωτήριος/ Βάσσιος, Βασίλειος


Institution and School/Department of submitter: ΤΕΙ Θεσσαλονίκης
Keywords: Fault Detection;External Testing System
Issue Date: Nov-2014
Publisher: SCIRP
Citation: Journal: Journal of Computer and Communications, vol.2, no.13, 2014
Papakostas, D., Vassios, V. and Pouros, S. (2014). Fault Tolerance Limits and Input Stimulus Selection using an Implemented FPGA-based Testing System. Journal of Computer and Communications [online]. 2(13), pp.18-24. Διαθέσιμο σε: http://www.scirp.org/journal/PaperInformation.aspx?PaperID=51506 [Ανακτήθηκε 19 Ιουλίου 2015]
Electronics and Circuits Conference, Beijing, 2014
Abstract: In this paper, the selection of fault tolerance limits and input stimulus using an implemented adaptive FPGA-based testing system based on a method utilizing wavelet transformation of the current waveforms is presented. The testing scheme is innovative because it offers the ability of applying different input stimulus signals with respect to the requirements of the examined circuit. Moreover, the method used is simple, offers a single-point test measurement solution and may easily be adapted to test various other analog and mixed-signal systems. Experimental results are presented showing the advantages of the proposed testing scheme.
Description: Δημοσιεύσεις μελών--ΣΤΕΦ--Τμήμα Ηλεκτρονικών Μηχανικών,2014
URI: http://195.251.240.227/jspui/handle/123456789/10049
ISSN: 2327-5227
2327-5219
Other Identifiers: 10.4236/jcc.2014.213003
Appears in Collections:Δημοσιεύσεις σε Περιοδικά

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